| 摘要 |
PURPOSE:To achieve high speed transfer, by permitting the readout from a sequential buffer memory for a specified amount of data write-in to the buffer memory. CONSTITUTION:The data write-in to a buffer memory (not shown) is made one after another to a corresponding address, according to the content of a write-in address counter WAC renewed with an ADD1 signal. During this time, an AND gate 11 is opened with a write-in/readout selection signal W/R, and when the write-in is finished, the output of a decoder 1c is at high level, a D-FF1b is set and a microprogram MP14 detects it. If data readout and transfer request are present, an AND gate 12 is opened with the signal W/R. On the other hand, the MP14 closes an AND gate 15 and opens an AND gate 16 and the content is given to a buffer memory BM while the content of the readout address counter RAC is renewed for data readout and transfer. |
