发明名称 |
FORMING METHOD OF FLATTENED WIRING LAYER |
摘要 |
PURPOSE:To make possible multiple wiring layers of IC by providing a flattened wiring layer having an upper surface nearly on the same level as a plane including the upper surface of an insulation layer, and an insulation layer having a reversed pattern of a wiring layer pattern that adjuacently connects to the side of a desired pattern on an insulation substrate. CONSTITUTION:A wiring layer W1 of pattern such as of Al and the same thickness of an insulation layer G1 are formed on an insulation substrate A. Then the surface H1 of the wiring layer W1 and the surface F1 of the insulation layer I1 are made with the same flat surface by scan etching the insulation layer on the wiring layer W1 by ion beam Q for etching consisting of Ar gas ion beam. The wiring layer W2 of the second layer and the insulation layer 12 are formed by the same process. Processing orders of the wiring layer and insulation layer may be changed for convenience sake. They may also be formed by scanning the depositing ion beam T of the wiring lay Z1 after forming the reversed pattern consisting of the insulation layer I1. |
申请公布号 |
JPS57134950(A) |
申请公布日期 |
1982.08.20 |
申请号 |
JP19810021300 |
申请日期 |
1981.02.16 |
申请人 |
NIPPON DENSHIN DENWA KOSHA |
发明人 |
HASEGAWA TACHIHIKO;ITOU HIROO |
分类号 |
H01L21/3205;(IPC1-7):01L21/88 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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