发明名称 |
SEMICONDUCTOR MEMORY CELL MARGIN TEST CIRCUIT |
摘要 |
A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V<ucc>u *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V<ucc>u *) is the semiconductor memory circuit main supply source (V<ucc>u) in normal operation but can be forced to a different voltage during the margin test. |
申请公布号 |
WO8202792(A1) |
申请公布日期 |
1982.08.19 |
申请号 |
WO1981US00136 |
申请日期 |
1981.02.02 |
申请人 |
MOSTEK CORP;OTOOLE JAMES E;PROEBSTING ROBERT J |
发明人 |
OTOOLE JAMES E;PROEBSTING ROBERT J |
分类号 |
G11C29/50;(IPC1-7):11C11/40 |
主分类号 |
G11C29/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|