| 摘要 |
Device means for reducing latch-back breakdown thus raising the reverse-biased power capability of a DMOS transistor or the like. A DMOS transistor is an MOS field effect transistor comprising a lightly-doped (usually diffused) body region formed in a drain region; a heavily-doped source region is located in the body region in proximity to the drain. Since such a device structure also exhibits substantial bipolar transistor action, it is prone to latch-back breakdown. Means for reducing latch-back breakdown include providing a distributed diode with a lower breakdown voltage than the DMOS transistor to non-destructively absorb reverse transients or by providing shunt conductance means for the diffused channel region to reduce both the voltage and the voltage gradient in the base of the parasitic bipolar device. These means may be used singly or in combination.
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