发明名称 MEASUREMENT OF SUPERPOSITION ACCURACY OF MASK FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To simply obtain the superposition accuracy of a mask for integrated circuit by a method wherein a plurality of test pattern layers are superimposed on a substrate for exposure and the dimension between each printed test pattern is measured. CONSTITUTION:The distance (a) between the first-layer test pattern 311, and the second-layer test pattern 32 and that (b) between the second-layer test pattern 32 and the first-layer test pattern 312 are measured by a microdimension measuring device. If these test patterns 311, 312, 32 are printed in accordance with design, a=b is established because the test pattern 32 is designed to be exactly located at the middle of the test patterns 311 and 312. On the other hand, if the test pattern 32 is printed by deviating by DELTAl, a=l+DELTAl, b=l-DELTAl are established to form anot equal to b. The DELTAl can be obtained by calculating (a-b)/2. If this way, superposition accuracy can simply be obtained by measuring the dimension between each test pattern.
申请公布号 JPS57132327(A) 申请公布日期 1982.08.16
申请号 JP19810016937 申请日期 1981.02.09
申请人 OKI DENKI KOGYO KK 发明人 TOUSAKA YASUROU;TANAKA YOSHIO;UCHIHO MITSUHISA
分类号 H01L21/027;H01L21/30;H01L21/66;(IPC1-7):01L21/30 主分类号 H01L21/027
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