发明名称 DIGITAL SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To prevent the generation of a noise due to an overflow by performing level clipping operation when an input digital signal overflows. CONSTITUTION:When a signal of the MSB of the output digital signal of a holding circuit 6 and a signal of the 2nd bit one bit higher than a bit constituting the 2nd bit of a final output differ in sign, an overflow occurs and the output signal of an exclusive OR circuit 13 has logic 0, so a data selector 14 performs switching to output a signal having a different sign from the MSB from an inverter 11 to input terminals A1-An-1. Thus, the overflow is detected securely to perform clipping without level variation, thereby preventing the generation of a noise.
申请公布号 JPS57132268(A) 申请公布日期 1982.08.16
申请号 JP19810017658 申请日期 1981.02.09
申请人 NIPPON VICTOR KK 发明人 KASUGA MASAO;TSUCHIKANE YOSHIYUKI
分类号 G06F7/38;G06F7/483;G06F7/508;G06F7/544;G06F17/10;G11B20/10;H03H17/02;H03H17/04;H04B14/04 主分类号 G06F7/38
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