发明名称 DIGITAL SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To prevent overflow, etc. of an input digital signal, by adding the input digital signal to a coefficient from a memory, amplifying a signal of other bit except MSB of an output signal of an adder, and also outputting a signal of MSB. CONSTITUTION:A digital signal of (n) bits, which has been applied to an input terminal 5 is applied and held in a holding circuit 6, and after that, is applied to a multiplier 7. On the other hand, a coefficient stored in a coefficient memory 8 is read out and attenuated 9, and the coefficient of (m) bits obtained by said attenuation is applied to a coefficient holding circuit 10 and is held. An output signal of (m) bits of this circuit 10 is applied to the multiplier 7. Subsequently, a digital signal of (n)+(m) bits is fetched from the multiplier 7, and is added 11 in case of finding the arithmetical mean. A signal of other bit except MSB among output digital signals of (n)+(m) bits of the adder 11 is supplied to an amplifier 12, by which it is amplified by an attenuation portion by the attenuator 9, and on the other hand, a signal of MSB is outputted directly to an output terminal 13.
申请公布号 JPS57132417(A) 申请公布日期 1982.08.16
申请号 JP19810017657 申请日期 1981.02.09
申请人 NIPPON VICTOR KK 发明人 KASUGA MASAO;TSUCHIKANE YOSHIYUKI
分类号 H03H21/00;G11B20/10;H03H17/02;H03H17/04;H04B14/04 主分类号 H03H21/00
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