| 摘要 |
PURPOSE:To reduce the missing of counting at a high speed counting rate, by receiving the input for simultaneous counting on only one side of opposing detectors or groups, and inhibiting it on the other side. CONSTITUTION:The output of the detector 1 (group a) becomes the input of an AND gate 3 and the input of a delay element 2. The output of the detector 1 which is delayed by said delay element 2 becomes the input of an AND gate 30. Meanwhile, the outputs of the detectors 11A (groups d and e) become the inputs of the AND gates 3 and 30 through an OR gate 9A. As a result, the entire simultaneously counted output 4 of the group a and d or e is obtained from the AND gate 3, and the accidental simultaneously counted output 5 is obtained from the AND gate 30 as a result of the delay in the delay element 2. |
