| 摘要 |
PURPOSE:To prevent a malfunction, by comparing timing signals with each other and generating a reset signal in case when there are signals generated at the same time, in case when plural timing signals different from each other are generated. CONSTITUTION:In an information processing device, timing signals T1-T3 different from each other are generated by controlling shift registers 1-3 by a write signal phi1 and a read-out signal phi2, but if any 2 timing signals become ''1'' at the same time, the information processor is disordered. In this case, if the signal T1 and T2 become ''1'' at the same time, an AND gate 9 becomes ''1'', and ''1'' is outputted to a resetting circuit 12 through an OR gate 10 and an OR gate 11. Subsequently, said signals are reset before the information processor executes a malfunction. |
