| 摘要 |
<p>PURPOSE:To make the synchronous operation of processors possible, by deciding whether return signals are transmitted simultaneously or not, based on whether the difference of the time to arrival of respective return signals from memories is in an allowable range or not in accordance with the access signal. CONSTITUTION:If a timing signal TX0 and return data DX0 of a memory MM0 arrive earlier than a timing signal TX1 and return data DX1 of a memory MM1 and the time difference between them is in an allowable range, a logical 1 appears at a terminal TRT1 because of the cross connection between circuits of system 0 and 1, and a seizing signal input TG of a timing generator TMG0 becomes logical 1 to start the generator TMG0. A signal terminal TRT0 of the circuit of the system 1 is logical 1. Then, a generator TMG1 for the return signal to a processor CP1 is started. Generators TMG0 and TMG1 are started simultaneously by the set of a flip flop TR1. If the time difference is outside the allowable range, generators TMG0 and TMG1 are not started, and return signals are returned.</p> |
