CONSTRUCTING A DELAY CIRCUIT FOR A MASTER SLICE IC

摘要

In a method of constructing a delay circuit in a master slice IC formed on a semiconductor substrate, the master slice IC comprises regularly arranged MIS transistors (Qn, Qp) having gate electrodes (61-66). The MIS transistors constitute various logic circuits. A delay circuit (DLY) is formed between two logic circuits (INV1, INV2) and comprises resistance and capacitance. The resistance is formed by the resistances of the gate electrodes by connecting sequentially (L6-L10) the gate electrodes (62-65) between the two logic circuits. The capacitor is formed by capacitances between the gate electrodes and the semiconductor substrate. By this connection, a small size and a precise delay time of a delay circuit can be obtained.