发明名称 RANDOM LOGIC TESTING FOR CMOSLSI
摘要 PURPOSE:To facilitate a check whether a logic has been realized ideally or not by a method wherein a circuit connection information is driven from a mask pattern information, the connection information is used for restoring a logical expression and thereafter the foregoing logical expression is compared with a logical expression being formed directly from the initial logical circuit diagram. CONSTITUTION:A C-MOSLISI circuit being completed is converted to a mask pattern for manufacturing a semiconductor device. Subsequently, a matrix is prepared by wiring-tracing the mask pattern and the connection information concerned with elements is extracted by using the matrix. Subsequently, the extracted connection information is simplified on the basis of a predetermined reference to rewrite into said structure. Subsequently, a logic expression suitable for N channel and P channel MOSFET respectively is prepared based on said structure and thereby the logical data is restored. Subsequently, the restored logical data is compared with and verified with the logical data made directly from an initial circuit, and confirmation is performed on whether an LSI layout design is correct or not to obtain a correct correspondence with each other.
申请公布号 JPS57130425(A) 申请公布日期 1982.08.12
申请号 JP19810015923 申请日期 1981.02.04
申请人 SHARP KK 发明人 NISHIMOTO TAKESHI;INUBUSHI TSUNEO
分类号 G01R31/28;G03F1/84;G06F17/50;H01L21/027;H01L21/30;H01L21/66 主分类号 G01R31/28
代理机构 代理人
主权项
地址