发明名称
摘要 <p>PURPOSE:To releave the missing clock interruption by the addition of a simple program, by checking the content of the watchdog timer during the idle period of computer and compulsively resetting the auxiliary flag register immediately before the time-up. CONSTITUTION:The content of the auxiliary flag register AFR consisting of the set of a plurality of FF circuits is given to the interruption register FR consisting of FF circuits through the OR gate OR. Each bit of the register AFR is set with clock pulse or interruption signal, and when either one bit of the register AFR is set for the signal, the signal is given to the register FR through the gate OR to set the interruption flag and the production of interruption is informed to the computer. Further, during the idle period of computer, the content of the watchdog timer is checked and the gate OR is controlled just before the time-up of the timer to reset the register FR compulsively, allowing to relieve the missing of clock without changing the existing hardware.</p>
申请公布号 JPS5737891(B2) 申请公布日期 1982.08.12
申请号 JP19790095496 申请日期 1979.07.26
申请人 发明人
分类号 G06F9/48;G06F1/04;G06F1/14;G06F9/46;G06F11/30 主分类号 G06F9/48
代理机构 代理人
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