发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To improve sense amplifier sensitivity by reducing noises, by activating adjacent sense amplifiers at different timing in one refreshment cycle. CONSTITUTION:To sense amplifiers S. A., (n) digit lines Di (i=0-n-1) are connected and the signal transfer of memory cells Cs connected to the digit lines Di is controlled by transistors (TR)Qw1 and Qw1. The signal transfer of a dummy cell Cs is controlled by TRs Q1 and QR2. Alternate common sources of the sense amplifiers are connected and TRs QS1 and QS1 hold the respective common source at a low potential. In one refreshment cycle, signals phiW1, phiR1 and phiS1, or phiW2, phiR2 and phiS2 for word line selection, dummy word line selection and sense amplifier activation are activated and alternate sense amplifiers only are activated at the same time.
申请公布号 JPS57130287(A) 申请公布日期 1982.08.12
申请号 JP19810016072 申请日期 1981.02.05
申请人 NIPPON DENKI KK 发明人 KANEKO SHIYOUJI
分类号 G11C11/409;G11C11/401;G11C11/4091 主分类号 G11C11/409
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