| 摘要 |
<p>PURPOSE:To reduce the size and weight of an entire automatic train control device and to simplify the circuit of the device by integrating a speed checking circuit and a circuit operation providing test circuit in a large scale integrated circuit. CONSTITUTION:Train speed information from a speed generator 1 is converted into a speed pulse fv, is then applied to a speed counter 5, which in turn produces a train speed data V. A buffer circuit 9 applies an automatic train control signal, information for wheel diameter and information concerning limit speed to an address setting circuit 10, thereby producing a limit speed data P from a memory circuit 11. The outputs of the circuits 10, 11 are checked by parity. In a diagnostic cycle, a pulse fvc cps is inputted to the circuit 10, and the various data are latched at the respective timings by external trigger signals by latch circuits 21-23 respectively.</p> |
