| 摘要 |
PURPOSE:To set a stop bit at an optional length, by switching a selector to a different frequency divider only in the case of the stop bit and supplying the output of the selector to a prescribed frequency divider. CONSTITUTION:A divider 2 divides the output of a clock generating circuit 1 down to 1/m (m>=1), and a divider 2B divides an input signal down to 1/2. Furthermore a divider 2C divides the input signal down to 1/n (n>=, mnot equal to n) and works only in the case of a stop bit SP. A selector 3 switches the output between the dividers 2A and 2C, and the output of the selector 3 is fed to the divider 2b. The selector 3 is controlled by a gate which uses a bit selection signal given from a terminal 4 and the signal given from a decoder 5 as an input. An output terminal 7 extracts the output of the divider 2B in the form of a transmitting timing signal. In such a way, a stop bit can be set at an optional length. |
