发明名称 DELAY ADJUSTING CIRCUIT OF NON-RETURN-TO-ZERO SIGNAL
摘要 PURPOSE:To simplify a circuit configuration and to maintain the stability of an operation, by constituting so that the element is constituted of a variable phase shifter having one control element, and a logical element, in a relative delayed extent adjusting circuit of an NRZ signal between multidigital transmissions in the digital transmission system. CONSTITUTION:A frequency dividing circuit 106 divides an input clock pulse 4 into (n), and the first pulse shaping circuit 101 shapes a waveform of an input NRZ signal 1 by the pulse 4. A series parallel converting circuit 104 makes a signal 2 of the circuit 101 branch to (n) rows by a clock pulse 7 of the circuit 106. A variable phase shifter 103 shifts and varies phase of the pulse 7 of the circuit 106. A parallel-series converting circuit 105 converts an NRZ signal 8 of the circuit 104 in reverse to one row by a clock pulse 9 of the phase shifter 103, and outputs an NRZ signal 3 havng a variable phase-shifting extent of (nXphi) (rad). An (n) multiplying circuit 107 multiplies the pulse 9 of the phase shifter by (n), and outputs a clock pulse 5.
申请公布号 JPS57129010(A) 申请公布日期 1982.08.10
申请号 JP19810015174 申请日期 1981.02.03
申请人 NIPPON DENKI KK 发明人 NAKAJIMA MASAHIRO;HASHIMOTO HIROMI
分类号 H04L25/40;H03H7/30;H03H11/26;H03K5/13;H03K5/135 主分类号 H04L25/40
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