| 摘要 |
PURPOSE:To reduce SN ratio, by providing a gate means by which a clock pulse of a comparatively high speed supplied to an external input terminal is made to a direct input signal, and operating a digital signal system circuit by the time required essentially, by the clock pulse selected by this gate means. CONSTITUTION:When a synchronizing pulse is inputted and the 9th input of a PCM output clock pulse is counted by a counting circuit 32, the subsequent input of the PCM clock pulse to all logical circuits excluding an input protecting circuit excluding an input protecting circuit 22 is inhibited automatically until a rise edge of the next synchronizing pulse is inputted. In this way, since all the logical circuits excluding the input protecting circuit 22 are made to a nonoperation state, generation of a digital noise from a PCM output controlling circuit 10 is suppressed. Also, since the SN ratio can be reduced, a change to IC is executed easily. |
