| 摘要 |
PURPOSE:To realize the higher resolution with a counter having less number of bits, by opening a gate circuit according to the AND conditions between a time width signal and a gate start commanding signal. CONSTITUTION:The main and auxiliary counters CWA and CWB in which a time width signal TW is set at H are ready for counting, and a flip-flop circuit FF is reset. Thus an AND gate is closed to apply no pulse train signal IND to the main counter CWA. The signal IND is applied only to the auxiliary counter CWB. When the counter CWB finishes to count a prescribed count value, an NAND circuit detects this to set the circuit FF and to open the circuit AND. Then the counter CWA starts to count the signals IND. In such a way, the higher resolution is obtained with a counter having less number of bits. |
