发明名称 CMOS TYPE MASK ROM
摘要 <p>PURPOSE:To obtain an easily manufactured mask ROM through which no standby current flows, by using desired enhancement and depletion type transistors (TR) in combination as parallel and series P and N type TRs of a decoder for selecting memory chips of N type TRs. CONSTITUTION:A decoding circuit for an N type TR memory chip selecting signal CS consists of series P type TRs 207-210 between a power source and selection lines and parallel-corrected N type TRs 211-214, etc., between the selection lines and earth, and the corresponding TRs 207-210, and 211-214 are driven by external chip selection signals CS10 and CS20 and signals CS10 and CS20 passed through inverters 203 and 204. When boron, etc., is injected into the gates of the TRs 207-214 to increase threshold voltages, enhancement and depletion type TRs are combined in accordance with a mask and since gates, etc., are not used, the need for a standby current is eliminated, thereby obtaining an easily-manufacture mask ROM which has low power consumption and simple constitution.</p>
申请公布号 JPS57123597(A) 申请公布日期 1982.08.02
申请号 JP19810007149 申请日期 1981.01.22
申请人 OKI DENKI KOGYO KK 发明人 NAKAMURA TSUNEO
分类号 G11C17/18;G11C11/41;G11C11/413;G11C17/12 主分类号 G11C17/18
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