| 摘要 |
PURPOSE:To carry out a test without limiting the port input/output function at a terminal, by producing a control signal for an input/output instruction in different timing in a test state. CONSTITUTION:The machine cycle signal is produced from a machine cycle signal generator 2 for execution of an instruction based on the clock signal CK produced from a clock generator 1. Thus the period is controlled for executing of the instruction inside an instruction executing device. For a general procedure for execution of an instruction program, an instruction which is previously written into a program ROM10 is delivered in a timing T1 to an internal data bus 20 via a buffer which is activated by the output signal supplied from an AND gate 3. This instruction is received at an instruction register IR30. Then a machine word received at an IR30 is interpreted by an instruction decoder 40 to produce various control signals in a prescribed timing respectively. |
