| 摘要 |
A method of manufacturing a one-transistor memory cell using the single silicon gate technique, using a bit line of doped material and a metal word line. Such memory cells have the disadvantage that increasing integration density is accompanied by transit time effects which undesirably reduce the working speed of the device. To avoid this disadvantage, the invention envisages that, after the gate oxidation, an implantation of electricity carriers of one polarity is carried out in the subsequent source and drain region of the selection transistor and of the storage capacitor and this implantation is completed either by an implantation or a diffusion of electricity carriers of the same polarity as in the first implantation in the course of a subsequent process step in the drain and source region. During the application of the silicon layer, contact is made to the doped bit line region with a polysilicon strip. The invention can be applied in memories having a high integration density such as, for example, in 262 kbit memories. <IMAGE> |
