发明名称 MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To execute an interruption of an optional shared device to an optional processor, by providing an interruption number table for recognizing the interruption of the shared device and discriminating the processor to be interrupted. CONSTITUTION:In case when an interruption has been generated from shared devices 4a, 4b, a bus controller 2' detects what has caused its interruption, by the same method of a processor, and senses its interruption number. After the interruption number has been recognized, an interruption number table 7 is referred to in order to discriminate to which processor an interruption request is executed. In the interruption table 7, the number of the processor to be interrupted is stored in accordance with the interruption number which has just been sensed, therefore, the processor number concerned is read out, and the interruption is executed to the processor concerned from the bus controller 2'. Accordingly, each processor 11-1n is capable of receiving an interruption from an optional shared device.
申请公布号 JPS57121726(A) 申请公布日期 1982.07.29
申请号 JP19810008171 申请日期 1981.01.21
申请人 MITSUBISHI DENKI KK 发明人 KAGAWA EIICHI
分类号 G06F13/14;G06F13/24;G06F15/16;G06F15/177 主分类号 G06F13/14
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