发明名称 TEST PATTERN OF INTEGRATED CIRCUIT
摘要 PURPOSE:To realize efficient use of a testing device, by storing the test patterns of >=2 different kinds of integrated circuits, in one test pattern area, in case when the number of integrated circuits to be measured is smaller than the number of measuring terminals of the testing device. CONSTITUTION:In 1-(m) channels and (m)+1-(n) channels (1<m<n) among test patterns of (n) channels, desired pattern information rows 1, 2 are written in an address 3. A generated test pattern is sent to a testing part 7 through a connecting line 8 from a testing device 9, by a control signal sent through a connecting line 10 from an operation console 11. The testing part 7 receives the control signal from the testing device 9, applies test pattern information to an integrated circuit to be measured 5, and tests the integrated curcuit 5 to be measured. In this way, since differenct kinds of test patterns can be stored in the same test pattern area, it is unnecessary to change a peripheral circuit at the time of selection in accordance with a characteristic of the integrated circuit 5 to be measured.
申请公布号 JPS57120870(A) 申请公布日期 1982.07.28
申请号 JP19810006871 申请日期 1981.01.19
申请人 NIPPON DENKI KK 发明人 MORINO HARUMI
分类号 G01R31/28;G01R31/317;G01R31/3183 主分类号 G01R31/28
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