| 摘要 |
PURPOSE:To make a high-speed operation possible, by connecting the output of an FF in the last stage of a shift register to the input of an FF in the first register and by setting the FF in the first stage and FFs in the second and following stages to states different from each other. CONSTITUTION:Four D (depletion) type FFs 11-14 are cascaded to constitute a shift register, and an output terminal Q of the FF14 in the last stage is connected to an input terminal D of the FF11 in the first stage. A clear signal is applied from a clear signal generating circuit 15 to a reset terminal S of the FF11 in the first stage and respective reset terminals of FFs 12-14 in the second and following stages to set the FF11 in the first stage and FF2 12-14 in the second and following stages to states different from each other. Clock pulses are applied to FFs 11-14, and the state of respective FFs is circulated. Consequently, since the output of each FF is inputted to the FF in the next stage directly, a high- speed operation is possible. |
