| 摘要 |
PURPOSE:To suppress in minimum the positioning error between a gate electrode and an impurity layer by forming a mask alignment pattern for indicating the position of the impurity layer formed locally. CONSTITUTION:A gate insulation film 31 has a double structure of such an insulation film as Si oxide film 34 and Si nitride film or the like. An impurity layer 33 for providing a threshold voltage VT2 ( >0) is formed by using a field film 31 for a mask. Subsequently, a photo resist 37 is formed so that the mask alignment pattern 38 of photo mask coincides with the mask alignment pattern 36 of the film 31. Subsequently, an impurity layer 41 for providing a thereshold voltage VT1 (<0) is formed by using a photo resist for a mask. In this time, an opening is provided for a mask alignment pattern 43, wich is formed on a region 39. Subsequently a step 44 is formed on the pattern 43. According to such a constitution, the mask alignment pattern 43 for indicating the position of the impurity layer 33 for providing the voltage VT1 is etched on a field film. Subsequently, a mask alignment pattern 46 is formed in response to the pattern 43 and a gate electrode 45 is formed by utilizing the pattern 46. Consequently, a position deviation of the electrode 45 is suppressed within the range of delta2. |
