发明名称 Address buffer circuit
摘要 An address buffer circuit is used in a memory device, for example in an EPROM device, and enables high speed testing of the memory device. The address buffer circuit can output "1" or "0" from both a positive output terminal and a negative output terminal when an input word address signal having a signal level different from the usual signal level is applied to an input of the address buffer circuit, so that a plurality of word lines can be selected at a time.
申请公布号 US4342103(A) 申请公布日期 1982.07.27
申请号 US19800171272 申请日期 1980.07.23
申请人 FUJITSU LIMITED 发明人 HIGUCHI, MITSUO;MIYASAKA, KIYOSHI
分类号 G11C11/41;G11C8/06;G11C8/12;G11C11/413;G11C17/00;G11C29/00;G11C29/34;G11C29/46;G11C29/50;(IPC1-7):G11C8/00 主分类号 G11C11/41
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