| 摘要 |
PURPOSE:To compress the scale of a hardware, by using a clock signal extracted from a low-order group signal on an input side as a readout clock signal. CONSTITUTION:The titled system is constituted in such way that not only a data by every bit is read out from a device 211 with the clock signal C1 extracted by a bipolar/unipolar converter B/U or a CMI code/unipolar converter C/U211, but also, the data by every bit is read out directly from a reception memory circuit 214 setting the clock signal C1 as the readout clock signal. Thus, by setting the clock signal C1 on the input side as a common readout clock signal for an input side bit and an output side bit, it is possible to make a PLL or a jitter absorbing buffer memory unnecessary.
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