Nonvolatile semiconductor memory circuits

摘要

An NMOS non-volatile latch having N-channel drivers Q1 and Q2 and variable threshold N-channel FATMOS transistors Q3 and Q4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X1 or X2) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.