Complementary metal-insulator semiconductor memory decoder.

摘要

A complementary metal-insulated semiconductor (CMIS) memory decoder (41) according to the invention is useful for a highly integrated large-capacity ROM or RAM. The CMIS memory decoder specifies each set of 2m (where m is positive integer) word lines [W0-W3] of a memory (40) to be accessed by the CMIS memory decoder. The decoder comprises 2m CMIS inverters (30, 31) for each set of the 2m word lines and also (2m-1) pull-down transistors (32) for each word line, the pull-down transistors being connected between ground (GND) and the corresponding word lines, the other (2m-1) word lines being connected to the gates of the pull-down transistors.