| 摘要 |
<p>A phase synchronizing circuit has a phase locked loop including a first phase comparison circuit (13) to which a predetermined input signal is supplied, a voltage controlled oscillator (VCO) (15) for producing an oscillation output the frequency of which is controlled by the output of the first phase comparison circuit, and first frequency dividing means (16, 17, 18) having at least a first frequency divider (16) to divide the output of VCO. The phase synchronizing circuit further includes second frequency dividing means (19, 20) for dividing the output frequency of VCO, a second phase comparison circuit (21) for comparing the phase of a first clock signal (fa') which is led from first dividing means, with that of a second clock signal (fa) which is led from second dividing means, and a controlling means for controlling the first frequency divider and second phase comparison circuit so as to synchronize phases of first and second clock signals. The controlling means controls the frequency dividing ratio of first frequency dividing circuit according to the phase difference between first and second clock signals in such a way that the frequency dividing ratio becomes 1/N, 1/(N+1) and 1/{[N+(N+1)]/2} wherein N is a positive integer. Phases of first and second clock signals can be synchronized accurately.</p> |
