| 摘要 |
PURPOSE:To unify input/output circuits and to execute the processing irrespective of a processing time, by coupling each microprocessor unit through a common bus, and providing an FI/FO memory circuit. CONSTITUTION:The SEND side is provided with a priority process-part 3-1 for controlling a transmission request signal REQ, an acknowledgement signal ACK and a system bus state signal BBSY, an FI/FO memory part 3-2 for storing a series of data, a block ready part 3-3 for showing a block data storing state, and a clock controlling part 3-4 for sending out data one by one. On the other hand, the REC side is provided with a part 3-5 for discriminating whether the system bus is in use or not, a signal checking part 3-6, an FI/FO memory part 3-7 for storing receiving data, and an interruption generating part 3-8 for making an MPU start to read. |
