| 摘要 |
PURPOSE:To achieve high-speed transfer, by simplifying logical circuits generating parity bits and logical elements performing check, through the addition of the parity bit to data and provision of a function making parity check at the peripheral device side. CONSTITUTION:Data and parity bits outputted from a main storage device 2 to a communication bus 1 are stored in a first-in and first-out system FIFO input buffer 105 through the control of a bus control section 107, by the readout request of a peripheral device controller 3a. A device adaptor 106 outputs data and parity bit to an internal bus 112 from the buffer 105 via an adaptor control section 108. A parity checker 110 compares the parity bit on a bus 12 with the bit in a parity bit generator 109 and sets internal FFs when errors are present. The data inputted to the adaptor 106 from peripheral devices 4a or 4b are outputted to a bus 112, bits are added with the generator 109 and outputted on a bus 1 via an output buffer 104. |
