| 摘要 |
<p>PURPOSE:To improve the data reading speed of a non-volatile semiconductor memory and to form ultrafine element by forming transistors for a memory cell and peripheral circuit in separated another semiconductor regions. CONSTITUTION:Two p-type well regions 12, 13 are isolated and formed in the surface region of a substrate 11. A pair of n<+>type regions 14, 15 becoming the drain and the source of an MOS transistor are formed at the prescribed interval on the surface region of one 12 of the well regions. A floating gate 16 and a control gate 17 form a double gate type MOS transistor with drain, source to become a memory cell. A pair of n<+>type regions 18, 19 becoming the drain and the source of an MOS transistor are formed at the prescribed interval on the surface region of the other 13 of the well regions. A gate 20 forms an MOS transistor with drain, source and peripheral circuit.</p> |
