| 摘要 |
<p>PURPOSE:To achieve stable intermittent run only with speed control, by taking the pulse width modulation output of phase control at still and slow motion reproduction as a signal with almost 50% of duty cycle. CONSTITUTION:A timing pulse generating circuit 23 generates a pulse delaying a reference signal G by a specified time. In the counting operation of a m-bit binary counter 24, it is reset with a pulse B and starts count just after the reset. Signals E, F synchronized with count values NL, NH (where; NL=X.2<n> and NH=(X+1).2<n>-1, and X is positive integer) of the counter 24 are generated at a gate signal generating circuit 25. While the count value D of the counter 24 is 0-NL, an output I of a gate group 27 is taken as ''0'', while NL-NH, gate groups 26, 27 are opened and the content of count of lower rank n-bit of the counter 24 is taken as the output I of the gate group 27, and when >=NH, the output I of the gate group 27 is taken as a constant value of 2<n-1>.</p> |
