Digital=to=analogue converter - resolution being nearly doubled by reducing repetition frequency of shift clock during register shift period

摘要

This D/A converter, which includes a shift register followed by an integrator, gives higher resolution without the need for increasing the number of register elements. This is achieved by progressively reducing the repetition frequency of the shift clock during a register shift period. This results in almost doubling the analogue data for the same number of elements. The shift register (SR) is clocked by a shift clock (TG) derived from a clock pulse (T), but whose repetition frequency decreases exponentially during one shift period as a result of the action of a counter (Ql-Qn) and OR-gates (Ul-Un). Principal application is for the control of brightness, volume, contrast and colour hue in radio and TV-receivers.