发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To increase the total processing speed by selecting an ROM when a CPU reads a program loader or an RAM when it loads a system program. CONSTITUTION:To a CPU2, input and output equipment 7, an address decoder 9, a register 10, and a memory 11, etc., are connected through a data bus 5 and an address bus 6. The memory 11 is provided with an RAM12, which has characteristic addresses, as chips 12a and 12a', and further provided with an ROM13, wherein a program loader is recorded, having the same addresses with the chip 12a'. Furthermore, a memory control circuit 15 is connected to the chip 12a' of the RAM12 and the ROM13. Consequently the controller 15 selects the ROM13 when the CPU2 reads the program loader or the ROM12 when it loads a system program, thereby increasing the processing speed.
申请公布号 JPS57113163(A) 申请公布日期 1982.07.14
申请号 JP19800187928 申请日期 1980.12.29
申请人 FUJITSU KK 发明人 NAKAMURA HIDEAKI
分类号 G06F9/445;G06F12/06 主分类号 G06F9/445
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