| 摘要 |
PURPOSE:To obtain a circuit free of access delay without justice to a device with high priority with regard to acceptance, by providing a fixed priority circuit which selects an access request, an access-request queuing register and a time-series display register. CONSTITUTION:For example, access request signals MRQ0-MRQ2 for access from central processors CC#0-CC#2 to a common storage device M are sent to a fixed priority circuit FRC through memory-request queuing flip-flops MRQ0F- MRQ2F. In accordance with fixed priority levels given to the respective devices through the AND gates AGF0-AGF2 of the fixed priority circuit FRC, the access request signals are sent selectively to a memory queuing register WR and a time-series display register TR. Then, the generation order of the access requests is registered and displayed through the flip-flops of the respective registers controlled by a clock, and storage-device control circuit MC is started. |
