| 摘要 |
PURPOSE:To control a large quantify of data by less hardware by returning the specific low-order digit part of an address, by counting the number of data in the order of elements, and by generating array gate control information from information for array and the number of data. CONSTITUTION:During parallel access, an initial data selector IDS outputs the A of rearrangement information (a) which corresponds to initial data to a bus (b), and it is sent to an adder ADD and a data significance control circuit DVC. Then, ''0''s are outputted following the initial data. The data significance control circuit DVC generates a significance signal (c) in accordance with the value of the (b) and whether the initial data is present or not, and the number of significant data is counted. A control signal from a memory access control circuit MAC includes a data transmission signal DOW-A, a signal for discriminating between the initial data and others, and the rearrangement information. The number of significant data is added and accumulated by a gate signal control circuit EN, and the resulting decoded signal (d) is used for bus switching by a gate signal. |
