| 摘要 |
PURPOSE:To make priority settable arbitrarily in multiple interruption signals by changing over the output of an interruption signal latching circuit to the address from a control circuit and outputting an interruption signal to a corresponding output line at the time of writing prioirty determining information to an RAM. CONSTITUTION:Interruption signal groups are held with a latch 2, and with the output thereof as an address of an RAM6, information is readh through a selector 4, and the one of the highest prioirty with respect to the interrution signals is outputted 9 via a decoder 8. This output 9 is inputted to a control circuit 10 as well which controls the latch 2, the selector 4 and the RAM6. Namely, the selector 4 is changed over by a changeover signal 11 to an address signal 13 for storage of data into the RAM to apply a write control signal 12 to the RAM, and a write data 14 is written to the address from the selector 4, whereby the priority determining information is set and the RAM is set in a call mode. Hence, in the case of changing the contents of the RAM, it is possible to change the priority for the interruption signals arbitrarily with the control circuit without changing packaging positions and the like. |
