| 摘要 |
PURPOSE:To increase not only the reliability but the availability, by securing a duouble structure for a memory to reduce the error. CONSTITUTION:Primary data memories 11-15 are provided along with alternate data memories 21-25, and the same data is written into these memories in the writing mode. Either one of these data is delivered via registers 81-85 to receive a parity checkthrough parity checking circuits 3 and 4. If an error is detected through the parity check, the output of the circuit 3 or 4 is preserved at a flip-flop 5 by a proper timing signal T. The output data is switched by the output the flip-flop 5 and then fetched into holding registers 81-85 after a delay of a certain time. |
