| 摘要 |
This arrangement has a memory (SP0, SP1) which, in the case of m envelope bits and n time slots, has at least 2.m.n memory cells and stores an equal number of bits of a multiplex signal. The sync bits of consecutive envelopes are identified with an envelope locator (E1, E2, E3, U1) and the address of the sync bits which is located in this way is recorded in a position memory (PSP). With the aid of the noted address and the use of an address computer, those modified read-out addresses are identified with which the individual bits of the envelope-interleaved time division multiplex signal can be read out. <IMAGE> |
