发明名称 REFRESH CONTROL SYSTEM
摘要 PURPOSE:To prevent the reduction of the travelling speed of a CPU, by performing the refresh plural times with every certain period during which the contents of a memory can be recovered and with an address unit larger than 2 units and less than N units. CONSTITUTION:An interval timer 9 delivers a refresh signal RFS to a bus control circuit 7 with period T4=T1/n to a certain period T1 during which the contents of a dynamic memory 5 can be recovered. The circuit 7 checks the state of occupancy of a bus line 3 by the signal RFS and occupies the line 3 if it is idle. Otherwise the line 3 is occupied as soon as the occupancy of the line 3 is cancelled. Then an RF start signal RST is delivered to an address counter 11 and an RF counter 12 of an RF circuit 10, and the start of the refresh RF is commanded to the circuit 10.
申请公布号 JPS57111881(A) 申请公布日期 1982.07.12
申请号 JP19800187935 申请日期 1980.12.29
申请人 FUJITSU KK 发明人 TANAKA TAKAO
分类号 G11C11/406 主分类号 G11C11/406
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