| 摘要 |
PURPOSE:To assure the accurate demodulation of a data, by freely selecting the pulse duration of a data window by a specific means to increase the lead margin when the signal recorded by an MFM modulating system is demodulated. CONSTITUTION:A DLX is formed with AND or OR gates, and the width of enlargement is decided for a data window by the number of these gates. The output of each AND side (positive signal) is terminated and connected to the gate of the next stage; and the output of each OR side (negative signal) is not terminated and connected to an SW. The other direction of the SW is connected to the negative signal side of the output of an FF4. A dot OR is obtained by a terminal attached to the negative signal side of the FF4 by properly connecting the SW. Thus the pulse duration can be freely selected. For the PRIFCLK, the DLNIF is delayed more in order to ensure the accurate blanking of the SPD, and at the same time the resynchronism is secured with the IFCLK through an FF7 to produce the NRZDT. |
