发明名称 MULTI-ADDRESS MEMORY CIRCUIT
摘要 PURPOSE:To enhance the function of a computer, by producing a multi-address memory system which is suited to a microcomputer, etc. which has high efficiency and a low price. CONSTITUTION:In the normal application mode, an address gate 54 for subject of alteration is opened and the CPU addresses #8(bit 8')-#15(bit 15) are used for the addresses of an RAM51 as they are. At the same time, the terminals CS and RD of the RAM51 are selected through OR circuits 57 and 58 plus an AND circuit 60 respectivey. Thus the RAM51 is read. When the cnverting contents of the address is altered, a flip-flop 6 is reset by the address on a data bus. Thus a contents altering address gate 52, a two-way data bus gate 55 and an AND circuit 59 are opened, and a decoder 56 is selected by the state of the address.
申请公布号 JPS57111873(A) 申请公布日期 1982.07.12
申请号 JP19800189307 申请日期 1980.12.27
申请人 RICOH KK 发明人 KURACHI SHIGEO;YAGI YOSHIO
分类号 G06F12/10;G06F12/02 主分类号 G06F12/10
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