发明名称 DECODING SYSTEM OF BINARY CODE
摘要 PURPOSE:To simplify the constitution of a hardware and to reduce the hardware quantity, by converting a 3-bit data into a 2-bit code. CONSTITUTION:The EFM signal supplied to a terminal 9 is turned into a parallel data output of 14 bits by a shift register 3. Each parallel output is converted into a parallel data of 10 bits by each of logical converters 11-14 of 3-bit input/2-bit output. This parallel data is supplied to a demodulator ROM15. The ROM15 consists of an input address of 10 bits and an output terminal of 8 bits and decodes the data of 10 bits in a single meaning to send it to a latching circuit 7. This data is held by a latching signal. Thus an EFM demodulated data is obtained at a latch output terminal 8.
申请公布号 JPS57111815(A) 申请公布日期 1982.07.12
申请号 JP19800188304 申请日期 1980.12.27
申请人 MITSUBISHI DENKI KK 发明人 FURUKAWA TERUO
分类号 H03M5/04;G11B20/14;H03M7/04;H03M7/14;H04L25/49 主分类号 H03M5/04
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