| 摘要 |
<p>Arrangement to destroy by erasing the information contents in data memories and program memories included in a data base installation, without destroying the equipment. An operation device (MO) is brought to activate a first group of parallelly working address generators (AD1-ADn), these generators successively generating and selecting all addresses in a memory (DS1-DSn) which is separately connected to each of the generators and which is part of a first memory group. Gate circuits (GD11-GDn4) are connected to the data inputs on each memory unit in this first memory group through which binary digits of the same logical level is written into the selected addresses of the memories irrespective of what is already written there. The operation device (MO) also activates a second group of parallelly working address generators (AP1-APn), these generators successively generating and selecting all addresses in a memory (PS1-PSn) which is separately connected to each of the generators, said memory being part of a second memory group. Gate circuits (GP1-GPn4) are connected to the data inputs of each memory unit in this second memory group through which circuits binary digits of the same logical level are written into the selected addresses of the memories. After completed erasing in said first and second memory group an activation signal is transmitted to a control device (L) which then indicates that the erasing is finished.</p> |
