A high-performance microprocessor system has a central processing unit which exhibits an independent address data path and an independent arithmetic logic unit (ALU) data path. Each of these is suitable for simultaneous processing during one clock period. The data paths are connected to a common input multiplexer in order to receive information from an information bus. A common bus register receives information from the input multiplexer and the common output multiplexer is connected in such a manner that it receives information from the bus register and other units in the data paths in order to supply the information to the information bus. The arithmetic logic unit data path exhibits a set of registers which contains at least one bidirectional shift register which is logically combined with another register in the set of registers. An internal counter forms a part of the arithmetic logic unit data path and supplies information both to the set of registers and to the arithmetic logic unit. The bus register is divided into at least two one-byte registers in order to allow a fast execution of byte commands. A control unit for the microprocessor system includes a programmable logic array (PLA) which exhibits at least one program for testing the microprocessor system function, together with a control line which is connected to a console of a system which includes the microprocessor system in order to enable the user to initiate system checks from the console. Data and programs in the microprocessing system are protected against access or modification by unauthorised users by means of a special function (abort function). The design of the arithmetic logic unit data path allows very fast floating-point arithmetic operations to be executed. It also permits much faster division operations than conventional microprocessors. The microprocessor system is advantageously accommodated in a single IC chip in TTL and IIL bipolar technology.
