| 摘要 |
PURPOSE:To realize application to even an input and output controller which requires high-speed data transfer by minimizing the processing interruption of a CPU, by limiting the processing interruption to only the time when the CPU uses a common signal bus. CONSTITUTION:A CPU1 is equipped with a main storage device 2 and an input and output controller 3 both connected to a common signal bus 4. Once the CC use display FF14 of the CPU1 is set, the CPU1 gains the right to use the bus 4 and inhibits a use request 5 from the controller 3 while a signal for CC in-use display 52 is outputted. Then, when the CPU1 does not use the bus 4 any more, an external use permission FF54 is set and a signal for use permission 6 is supplied to the controller 3. Even if a use request 11 is generated by the CPU1 during the period, the FF14 is inhibited from being set because the FF52 is set. As the use request 5 for the bus 4 from the controller 3 ends, the FF52 is reset and the FF14 is set, giving the CPU1 the right to use the bus 4. |
