发明名称 ALTERNATE MEMORY CHECK SYSTEM
摘要 PURPOSE:To achieve effective test for alternate memory and alternate operation, by providing an information inverting circuit on an alternate memory write-in information bus and confirming the selection of content of alternate memory readout information bus at test. CONSTITUTION:After an arbitrary bit on a write-in information bus 1 is inverted from a normal state and written in a normal memory 2, the readout informtion of the memory 2 is checked at a circuit 8, and the error bit location is stored in an alternate bit location storage register 9. Next, the normal information is written in the memory 2, an inverting control line 16 turns on relating to the bit location stored in the register 9 and the inverted information is written in the alternate memory 7 through an alternate write-in information inverting circuit 15. At the readout state of the memories 2, 7, the information on a bus 11 is selected relating to the bit location stored in the register 9 and the error is detected at the circuit 8. Next, the line 16 and the circuit 15 are kept off to make readout/write-in for the memories 2, 7, allowing to confirm the normality of the memory 7.
申请公布号 JPS57109199(A) 申请公布日期 1982.07.07
申请号 JP19800186812 申请日期 1980.12.26
申请人 FUJITSU KK 发明人 IIJIMA KIYOKATSU;TANIGUCHI SHIYOUZOU;SAKURABA TAKAHIRO
分类号 G06F12/16;G06F11/20;G06F11/22;G11C29/08 主分类号 G06F12/16
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